Typically, memory devices, such as static random access memory (SRAM) devices, consume power during activation, such as when switching from a data retention mode into an operational mode for writing to the memory devices or when coupling power to the memory devices to enter a write-assist mode. This is because the virtual power (e.g., VDDI) and ground (e.g., VSSI) voltages are brought up to an operational level, i.e., a larger potential difference is coupled across the bit cell array of the memory device to make the bit cells operational. Power is consumed when the cells are charged or discharged to a higher potential defined between voltages VDD/VSS, respectively. The active power consumption depends on the capacitance of the entire circuit coupled between the VDDI/VSSI nodes, which is charged when the power supply voltages are applied.
When the memory device is switched from the retention mode to the operational mode, the entire bit cell array of the memory devices may be switched into the active mode and consume power in becoming operational, even if, for example, only one row of bit cells actually is being accessed for updating their content or the like. This results in large power consumption when switching and also static power consumption while remaining in the operational mode. Currently, the issue can be addressed with a Local IO (LIO) circuit that selects an active memory area to be powered. But a full function LIO occupies huge circuit area, which is not desirable.
An improved technique for selectively charging and powering bit cells in a memory device design would be advantageous.